This post is incomplete. Would update later... ;)
Address space of a process can exceed physical memory using virtual memory.
I can use the addresses in the secondary memory for realisation of a memory space bigger than that is available in terms of SDRAM on the embedded system.
Multiple processes resides in main memory, each process with its own address space.
Only active code and data is actually in the memory
Another property provided through that of virtual memory is protection. One process should not interfere with another process. Because they operate in different address spaces. This we can make sure once we have implemented virtual memory. Because then we have a clear partitioning of address spaces of different processes.
User process cannot access privileged information. because different sections of address space have different permissions.
So the big question comes... How is virtual memory realised ?
Using primarily Memory Management Unit.
This is provided with many of these modern micro-controllers which are targeted for use in embedded applications.
Segmentation based memory management
Segmentation is primarily provided by the simple MMU
A program running in 8086 can make use of four logical segments.
Program views its memory as a set of segments. ( Code, stack, Data, Extra ). Each program has its own segments. So these clearly defines different address space for different set of processes. Each access to memory is via a segment selector and an offset with in the segment.
All these things permits a program to have its own private view of memory and to exist transparently with other programs in the same memory space.
The whole infrastructure which is provided by the MMU will ensure that such access are really denied.
So the address generation is through this process. --segment based address generation--
The address in which the cpu generates can be consisting of two parts
Segment selector : which actually indicate the segments
Logical address : which is an offset in the segment.
Segment selector is used to access the base address of the segment in Segment Descriptor table. Notable thing is bound because each segment can be associated with a fixed size. Once we do this sum offset + base, that should not exceed bound of the segment. If it exceeds then access fault. This is an internally generated exception which is to be handled by the operating system. This mechanism ensures that each segment has been clearly separated out. And we cannot access beyond the segment boundary.
Next way to implement virtual memory is by the use of Paging.
The core concept is logical memory area can be larger than the physical memory.
Logical memory can be accommodated in the secondary storage.
Divide physical memory into equal sized chunks. And these chunks are called pages.
Any chunk of virtual memory is assigned to any chunk of physical memory. That is the basic principle of paging for implementation of virtual memory.
The secondary storage is also divided in terms of chunks or pages. And I have space for few pages in the primary memory. Conceptually it is very similar to that of cache blocks.
The difference between segmentation and paging is what ? Segmentation can be of arbitrary length while pages are chunks of fixed length.
page figure
Page Table : representation of the storage area required by a process. Here there are P pages for a process. So a process is divided into P pages. Information about all these pages are to be maintained in a page table. All these pages belonging to a process are not necessary reside in the main memory. Some are in physical memory. Another important thing is that pages can be accommodated anywhere in the memory. Not required to be stored at contiguous locations in the memory.
Entries in the page table is actually managed by the operating system.
Then we have page fault: which occurs when cpu generated an address which is not in memory. So memory exception occurs. So the handler is invoked to move data from disk or sec storage in to memory.
ARM has also got corresponding exception and corresponding mode to handle these kind of exception. So the current which generate this exception cannot execute. It has to be suspended, but since it is multitasking system other processes can be resumed and executed. In fact OS manages this.
Servicing a page fault
figure
Processor signals controller
read block of length p starting at disk address x and store at memory starting at address y
^This is the action that is actually taken care by the exception handler. coz this is what is told to the controller(I/O Controller which is managing the disk ). IO controller takes the data from the disk and once the data has been obtained a DMA is requested. DMA is executed under control of IO controller. Once the DMA is over the IOcontroller interrupts the processor. So the process which was suspend due to page fault can be resumed. Resuming means that it can be put into an active or ready queue.
Managing multiple processes
each process has its own virtual address space
each process has its own pge table.
In fact under that condition every program can start at the same (virtual address). Page table contains information about where that virtual address has been mapped in the physical memory. All the protection information now will be associated with the pages.
So for each process it can have its own page table and there would b permissions associated with pages.
Protection figure.
how is the page address really transilated.
The basic principle is same as that of the segmentation
In majority of the mordern microcontrollers which are used the MMU supports paged memory and page tables associated with individual processes.
Page table operations.
1 translation.: coz we hv seperate set of page tables per processes.
virtual page number forms index into page table ( points to a page table entry )
2 compute physical address:
page table entry provides information about page
if valid bit == 1 page is in the memory
use physical page number (PPN) to construct the address.
if valid bit == 0 then page is in the disk
page fault
must load page from disk into the memory before continuing
3 checking protections
access rights fields read only, read write, execute only
typically supports multiple protection modes ( kernel vs user )
Integrate virtual memory and cache
picture
segmentation is a logical unit visible to the user's program and id of arbitary size whereas paging is a physical unit invisible to the user's view and is of fixed size
What cpu generated is logical address which is being translated by the page table which is under hardware control of MMU and under software control of operating system. This translation unit is actually generating the physical address. Now for finding out whether there is a cache hit or miss this physical address is to be used. And the PHY address, what is being generated by the translation unit is the input to the cache controller. Here we have not shown the cache controller, we have just shown the cache. Now if there is a miss then we have to load the main memory to the cache. otherwise you have a hit and you get the data from the cache.
Where will be page tables really stored ? Because when I am using the translation you have to access the page table. Otherwise you cannot do translation from logical address to the physical address. Typically page table would be somewhere in the main memory. MMU cannot really store the page table. So an access to each location therefore implies access to main memory. Then you are actually defeating in that case the basic purpose of cache. There has to be some architectural innovation to overcome this problem.
Make the page table entries cached. Since look up involves memory access it is no longer efficient. So make page table entries cached.
So we have the concept of Translation Lookaside Buffer.
a small H/W cache in MMU.
it can also be in L1 cache as well. but in many cases it is a H/W cache in MMU.
which maps virtual page numbers to physical page numbers.
contains complete page table entries for small number of pages.
There has to be a caching policy for this pages as well.
TLB PICTURE
cpu generates the virtual address
TLB: if there is a miss in TLB, then I have to get that data either from the cache or from the main memory. So I may have part of the page table stored in the cache and remaining part may be stored in this TLB. And then I will do the translation. TLB is nothing but a page table entry put into cache.
Miss || has got two kind of significance.
page table content itself can be missing from the cache.
else it can be actually entry in the page table missing because that block has not been loaded as of yet. Why these two kind of miss in we can understand gradually.
First lets look at the basic translation procress
PICTURE
Big Picture
ARM core comes with MMU to support virtual memory. The primary motivation of providing this kind of MMU capablity is not only to have demand paging but most importantly to implement protection.
Like any other MMU, ARM MMU performs these tasks.
Address space of a process can exceed physical memory using virtual memory.
I can use the addresses in the secondary memory for realisation of a memory space bigger than that is available in terms of SDRAM on the embedded system.
Multiple processes resides in main memory, each process with its own address space.
Only active code and data is actually in the memory
Another property provided through that of virtual memory is protection. One process should not interfere with another process. Because they operate in different address spaces. This we can make sure once we have implemented virtual memory. Because then we have a clear partitioning of address spaces of different processes.
User process cannot access privileged information. because different sections of address space have different permissions.
So the big question comes... How is virtual memory realised ?
Using primarily Memory Management Unit.
This is provided with many of these modern micro-controllers which are targeted for use in embedded applications.
Segmentation based memory management
Segmentation is primarily provided by the simple MMU
A program running in 8086 can make use of four logical segments.
Program views its memory as a set of segments. ( Code, stack, Data, Extra ). Each program has its own segments. So these clearly defines different address space for different set of processes. Each access to memory is via a segment selector and an offset with in the segment.
All these things permits a program to have its own private view of memory and to exist transparently with other programs in the same memory space.
The whole infrastructure which is provided by the MMU will ensure that such access are really denied.
So the address generation is through this process. --segment based address generation--
The address in which the cpu generates can be consisting of two parts
Segment selector : which actually indicate the segments
Logical address : which is an offset in the segment.
Segment selector is used to access the base address of the segment in Segment Descriptor table. Notable thing is bound because each segment can be associated with a fixed size. Once we do this sum offset + base, that should not exceed bound of the segment. If it exceeds then access fault. This is an internally generated exception which is to be handled by the operating system. This mechanism ensures that each segment has been clearly separated out. And we cannot access beyond the segment boundary.
Next way to implement virtual memory is by the use of Paging.
The core concept is logical memory area can be larger than the physical memory.
Logical memory can be accommodated in the secondary storage.
Divide physical memory into equal sized chunks. And these chunks are called pages.
Any chunk of virtual memory is assigned to any chunk of physical memory. That is the basic principle of paging for implementation of virtual memory.
The secondary storage is also divided in terms of chunks or pages. And I have space for few pages in the primary memory. Conceptually it is very similar to that of cache blocks.
The difference between segmentation and paging is what ? Segmentation can be of arbitrary length while pages are chunks of fixed length.
page figure
Page Table : representation of the storage area required by a process. Here there are P pages for a process. So a process is divided into P pages. Information about all these pages are to be maintained in a page table. All these pages belonging to a process are not necessary reside in the main memory. Some are in physical memory. Another important thing is that pages can be accommodated anywhere in the memory. Not required to be stored at contiguous locations in the memory.
Entries in the page table is actually managed by the operating system.
Then we have page fault: which occurs when cpu generated an address which is not in memory. So memory exception occurs. So the handler is invoked to move data from disk or sec storage in to memory.
ARM has also got corresponding exception and corresponding mode to handle these kind of exception. So the current which generate this exception cannot execute. It has to be suspended, but since it is multitasking system other processes can be resumed and executed. In fact OS manages this.
Servicing a page fault
figure
Processor signals controller
read block of length p starting at disk address x and store at memory starting at address y
^This is the action that is actually taken care by the exception handler. coz this is what is told to the controller(I/O Controller which is managing the disk ). IO controller takes the data from the disk and once the data has been obtained a DMA is requested. DMA is executed under control of IO controller. Once the DMA is over the IOcontroller interrupts the processor. So the process which was suspend due to page fault can be resumed. Resuming means that it can be put into an active or ready queue.
Managing multiple processes
each process has its own virtual address space
each process has its own pge table.
In fact under that condition every program can start at the same (virtual address). Page table contains information about where that virtual address has been mapped in the physical memory. All the protection information now will be associated with the pages.
So for each process it can have its own page table and there would b permissions associated with pages.
Protection figure.
how is the page address really transilated.
The basic principle is same as that of the segmentation
In majority of the mordern microcontrollers which are used the MMU supports paged memory and page tables associated with individual processes.
Page table operations.
1 translation.: coz we hv seperate set of page tables per processes.
virtual page number forms index into page table ( points to a page table entry )
2 compute physical address:
page table entry provides information about page
if valid bit == 1 page is in the memory
use physical page number (PPN) to construct the address.
if valid bit == 0 then page is in the disk
page fault
must load page from disk into the memory before continuing
3 checking protections
access rights fields read only, read write, execute only
typically supports multiple protection modes ( kernel vs user )
Integrate virtual memory and cache
picture
segmentation is a logical unit visible to the user's program and id of arbitary size whereas paging is a physical unit invisible to the user's view and is of fixed size
What cpu generated is logical address which is being translated by the page table which is under hardware control of MMU and under software control of operating system. This translation unit is actually generating the physical address. Now for finding out whether there is a cache hit or miss this physical address is to be used. And the PHY address, what is being generated by the translation unit is the input to the cache controller. Here we have not shown the cache controller, we have just shown the cache. Now if there is a miss then we have to load the main memory to the cache. otherwise you have a hit and you get the data from the cache.
Where will be page tables really stored ? Because when I am using the translation you have to access the page table. Otherwise you cannot do translation from logical address to the physical address. Typically page table would be somewhere in the main memory. MMU cannot really store the page table. So an access to each location therefore implies access to main memory. Then you are actually defeating in that case the basic purpose of cache. There has to be some architectural innovation to overcome this problem.
Make the page table entries cached. Since look up involves memory access it is no longer efficient. So make page table entries cached.
So we have the concept of Translation Lookaside Buffer.
a small H/W cache in MMU.
it can also be in L1 cache as well. but in many cases it is a H/W cache in MMU.
which maps virtual page numbers to physical page numbers.
contains complete page table entries for small number of pages.
There has to be a caching policy for this pages as well.
TLB PICTURE
cpu generates the virtual address
TLB: if there is a miss in TLB, then I have to get that data either from the cache or from the main memory. So I may have part of the page table stored in the cache and remaining part may be stored in this TLB. And then I will do the translation. TLB is nothing but a page table entry put into cache.
Miss || has got two kind of significance.
page table content itself can be missing from the cache.
else it can be actually entry in the page table missing because that block has not been loaded as of yet. Why these two kind of miss in we can understand gradually.
First lets look at the basic translation procress
PICTURE
Big Picture
ARM core comes with MMU to support virtual memory. The primary motivation of providing this kind of MMU capablity is not only to have demand paging but most importantly to implement protection.
Like any other MMU, ARM MMU performs these tasks.
- translate virtual address to physical address
- Controls memory access permission
- determines behaviour of cache and write buffer for each page in memory
When MMU is disabled all virtual address will map one-to-one to the same physical address. So that means for a simple system you have a provision to disable MMU. So 32 bit address which arm generates will be mapped onto directly physical address.
MMU will only abort on translation permission and domain faults so these are the exceptions that MMU would generate under rare conditions.
Configuration and control components in the MMU
- Page tables
- TLB
- Domain and access permission (concept of domain is used in arm to define permissions )
- cache and write buffer ( how they are to be configured )
- CP15:c1 control register ( manages the MMU it provides a management interface to the MMU )
- Fast context switch extension ( additional H/W are there to provide FCS )
TLB: the provision for that is there in ARM MMU
