arm assembly work book { incomplete }

This is some of my rough works.
adc r2, r0, r1  ; r2 = r0 + r1 + carry bit

Arm architecture reference manual.pdf is a good reference for to learn ARM Architecture.

The subroutine return is performed by copying R14 back to the program counter.
This is typically done in one of the two following ways:
MOV PC,LR
BX LR



Arm LDM and SDM instructions
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch02s08s01.html
Syntax: LDM{cond}address-mode Rn{!},reg-list{^}
cond - Add an S suffix to an ARM data processing instruction to make it update the ALU status flags in the CPSR.
Rn - base register
! - specifies base register write back. If this is specified, the address in the base register is updated after the transfer. It is decremented or incremented by one word for each register in the register list.
register list - {r0,r1,r4-r6,pc}
address-mode: IA, IB, DA, DB.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/Cacdibae.html

Implementing stacks with LDM and SDM
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/Cacdibae.html

Stacking registers for nested subroutines
subroutine  STMFD   sp!, {r5-r7,lr} ; Push work registers and lr
            ; code
            BL      somewhere_else
            ; code
             LDMFD   sp!, {r5-r7,pc} ; Pop work registers and pc
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/Cacdibae.html

When an exception occurs...

When an exception occurs, the banked versions of R14 and the SPSR for the exception mode are used to
save state as follows: ( this we don't have to do )
R14_exception_mode = return link
SPSR_exception_mode = CPSR
CPSR[4:0] = exception mode number
CPSR[5] = 0 /* Execute in ARM state */
if exception_mode == Reset or FIQ then
     CPSR[6] = 1 /* Disable fast interrupts */
     /* else CPSR[6] is unchanged */
CPSR[7] = 1 /* Disable normal interrupts */
PC = exception vector address


an interrupt handler that wishes to store its return link on the stack might use instructions of
the following form at its entry point:
SUB R14, R14, #4
STMFD SP!, {, R14}
and return using the instruction:
LDMFD SP!, {, PC}^

When a SWI is executed, the following happens:

• SVC mode is entered
• R15 is saved in R14_SVC
• The IRQ disable bit is set
• The PC is set to address &0000008